SPI USER control register
| SPI_DOUTDIN | Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_QPI_MODE | Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. |
| SPI_OPI_MODE | Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. |
| SPI_TSCK_I_EDGE | In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. |
| SPI_CS_HOLD | spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_CS_SETUP | spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_RSCK_I_EDGE | In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. |
| SPI_CK_OUT_EDGE | the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. |
| SPI_FWRITE_DUAL | In the write operations read-data phase apply 2 signals. Can be configured in CONF state. |
| SPI_FWRITE_QUAD | In the write operations read-data phase apply 4 signals. Can be configured in CONF state. |
| SPI_FWRITE_OCT | In the write operations read-data phase apply 8 signals. Can be configured in CONF state. |
| SPI_USR_CONF_NXT | 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. |
| SPI_SIO | Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_USR_MISO_HIGHPART | read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_USR_MOSI_HIGHPART | write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. |
| SPI_USR_DUMMY_IDLE | spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. |
| SPI_USR_MOSI | This bit enable the write-data phase of an operation. Can be configured in CONF state. |
| SPI_USR_MISO | This bit enable the read-data phase of an operation. Can be configured in CONF state. |
| SPI_USR_DUMMY | This bit enable the dummy phase of an operation. Can be configured in CONF state. |
| SPI_USR_ADDR | This bit enable the address phase of an operation. Can be configured in CONF state. |
| SPI_USR_COMMAND | This bit enable the command phase of an operation. Can be configured in CONF state. |